5-Level Paging and 5-Level EPT White Paper
coll.
This document describes planned extensions to the Intel 64 architecture to expand the size of addresses that can be translated through a processor’s memory-translation hardware.
Retrieved from https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf on 2017 May 09.
Retrieved from https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf on 2017 May 09.
Рік:
2016
Видання:
Revision 1.0
Видавництво:
Intel Corporation
Мова:
english
Сторінки:
26
Серії:
Document Number: 335252-001
Файл:
PDF, 195 KB
IPFS:
,
english, 2016